Michigan spawns world's sleepiest chip

You’ve got to envy semiconductors. No, really. They don’t just sleep. They enjoy “extreme sleep”. In fact, a new chip which has sprung from the brains of the University of Michigan sleeps 30,000 better than its counterparts when it’s not being used and 10 times better when it is. That’s a lot of good sleeping right there.

Chipmakers are going crazy right now for cutting the energy their products use to win environmental brownie points, but the University of Michigan guys and gals reckon they’ve cracked the power conundrum with their new Phoenix chip.

According to the Uni:

The chip consumes just 30 picowatts during sleep mode. A picowatt is one-trillionth of a watt. Theoretically, the energy stored in a watch battery would be enough to run the Phoenix for 263 years.

The low power chips could turn up in “medical implants, environment monitors or surveillance equipment” according to the Uni – areas where you might want to stick a chip in but not have to replace the battery powering it for years and years and years. Like your chest.

From the Uni:

A group of U-M researchers is putting the Phoenix in a biomedical sensor to monitor eye pressure in glaucoma patients. Engineers envision that chips like this could also be sprinkled around to make a nearly invisible sensor network to monitor air or water or detect movement. They could be mixed into concrete to sense the structural integrity of new buildings and bridges. And they could power a robust pacemaker that could take more detailed readings of a patient’s health, researchers say.

Greenbang thinks this might be cooler than a rabbit that can tap dance.

And a little more on how the tech works:

A unique power gate design is an important part of the sleep strategy. Power gates block the electric current from parts of a chip not essential for memory during sleep.

In typical state-of-the-art chips, power gates are wide with low resistance to let through as much electric current as possible when the device is turned on. These chips wake up quickly and run fast, but a significant amount of electric current leaks through in sleep mode.

Phoenix engineers used much narrower power gates that restrict the flow of electric current. That strategy, coupled with the deliberate use of an older process technology, cut down on energy leaks.

“A power gate of such a small size is unheard of in traditional design since it severely limits the performance of the chip,” Seok said.

To address this performance loss, the Michigan team increased the chip’s operating voltage, increasing the baseline power by approximately 20 percent when the chip is awake. But Phoenix still runs at 0.5 Volts, rather than the 1 to 1.2 Volts typical chips require.